When a semiconductor drive circuit is used to drive a power conversion apparatus such as an inverter, the switching devices of the upper and lower arms are driven by using a pulse transformer that is configured to generate voltages of opposite polarities between the gate and source of the switching device of the upper arm and between the gate and source of the switching device of the lower arm. Specifically, rectangular-wave voltages +Vts [V]→0[V]→−Vts [V]→0 [V] are repeatedly applied between the terminals of the upper arm pulse transformer secondary winding and rectangular-wave voltages −Vts [V]→0[V]→+Vts [V]→0 [V] are repeatedly applied between the terminals of the lower arm pulse transformer secondary winding with the same timing.
The period during which the switching devices are in the OFF state in the period in which the voltage between the terminals of the upper arm pulse transformer secondary winding and the voltage between the ends of the lower arm pulse transformer secondary winding are both 0 [V] is called a “dead time”. The dead time is a period that is essential for preventing the short circuit between the upper and lower arms. Assuming that the length of the period in which the rectangular-wave voltage is at +Vts [V] or −Vts [V] is 50, for example, the length of the period of 0 [V] has to be set at approximately 1 to 2.
Patent Literature 1 is known as a circuitry technology for stably securing the dead time in cases where MOSFETs using Si semiconductors are driven. In this technology, the electric current path for charging the input capacitance (Ciss) at the time of turning ON and the electric current path for the discharge from the input capacitance at the time of turning OFF are separated from each other by use of a diode or the like. Further, elements such as resistors are arranged in the circuit so that the impedance of the charging current path becomes lower than that of the discharging current path. With such a configuration, the turn-on time is relaxed (increased) and the turn-off time is decreased (turn-off speed is increased) so as to stably secure the dead time.
Meanwhile, switching devices (junction FETs, metal-oxide-semiconductor FETs (MOSFETs), bipolar junction transistors (BJTs), high-electron-mobility transistors (HEMTs), etc.) using a wide band gap semiconductor such as silicon carbide (SiC), gallium nitride (GaN) or diamond are being brought into practical use in recent years.
Since such switching devices are formed by using a wide band gap semiconductor of high breakdown voltage, the semiconductor layer thickness in the voltage application direction can be reduced and excellent properties such as low conduction resistance can be achieved.
On the other hand, the reduction in the semiconductor layer thickness shortens the distances between the source/drain/gate electrodes and is causing an increase in parasitic capacitance inside the device (gate-drain capacitance (Cgd), gate-source capacitance (Cgs), drain-source capacitance (Cds)). As a result, the switching time for the turning ON/OFF increases due to the increase in the input capacitance (Ciss=Cgd+Cgs).
Circuitry described in Patent Literature 2 is capable of reducing the turn-off time (increasing the turn-off speed) by setting the gate-source voltage of the junction FET at the time of turning OFF at a negative voltage by use of a capacitor 15a.
However, trouble occurs when the voltage between the terminals of the pulse transformer changes from −Vts [V] to 0 [V] in a state in which electric potential making the gate's side of the capacitor 15a be the positive side is remaining at the terminals of the capacitor 15a due to a factor like a too short OFF period. In this state, due to the application of the voltage via the capacitor 15a, positive voltage is applied between the gate and the source of the junction FET, causing the turn ON action of the junction FET and making it difficult to stably secure the dead time.
A configuration capable of adjusting the turn-on time and the turn-off time by separating the gate current path at the time of turning ON from the gate current path at the time of turning OFF is illustrated in FIG. 7 of the Patent Literature 2. However, due to the addition of a diode 16a, no potential difference occurs between the terminals of the capacitor 15a shown in FIG. 7 in cases where the ON period is long. Therefore, since the gate-source voltage of the switching element cannot be set negative at the time of turning OFF and the reduction of the turn-off time (increase of the turn-off speed) is impossible, it has been difficult to stably secure the dead time.